The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Sep. 23, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Ngai Ngai William Hung, San Jose, CA (US);

Dhiraj Goswami, Wilsonville, OR (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/34 (2020.01); G06F 11/26 (2006.01); G06F 21/76 (2013.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G06F 11/261 (2013.01); G06F 11/3652 (2013.01); G06F 21/76 (2013.01);
Abstract

A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.


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