The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2023
Filed:
Apr. 15, 2022
Xilinx, Inc., San Jose, CA (US);
Juan J. Noguera Serra, San Jose, CA (US);
Tim Tuan, San Jose, CA (US);
Javier Cabezas Rodriguez, Austin, TX (US);
David Clarke, Dublin, IE;
Peter McColgan, North Dublin, IE;
Zachary Blaise Dickman, Dublin, IE;
Saurabh Mathur, Saratoga, CA (US);
Amarnath Kasibhatla, Sunnyvale, CA (US);
Francisco Barat Quesada, Dublin, IE;
Xilinx, Inc., San Jose, CA (US);
Abstract
An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.