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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11847452 B1

PDFFull Text
Date of Patent:
Dec. 19, 2023

Filed:

Jun. 28, 2021

Systems, methods, and apparatus for tile configuration

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Menachem Adelman, Haifa, IL;

Robert Valentine, Kiryat Tivon, IL;

Zeev Sperber, Zikhron Yaakov, IL;

Mark J. Charney, Lexington, MA (US);

Bret L. Toll, Hillsboro, OR (US);

Rinat Rappoport, Haifa, IL;

Jesus Corbal, King City, OR (US);

Dan Baum, Haifa, IL;

Alexander F. Heinecke, San Jose, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Yuri Gebil, Nahariya, IL;

Raanan Sade, Kibutz Sarid, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

NICHOLSON DE VOS WEBSTER & ELLIOTT, LLP

Primary Examiner:

Eric Coleman

Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 17/16 (2006.01); G06F 7/76 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/3016 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01);
Abstract

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

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