The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jun. 12, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nabajit Deka, Bangalore, IN;

Riccardo Mariani, Calci, IT;

Asad Azam, El Dorado Hills, CA (US);

Roger May, Banbury, GB;

Prashanth Gadila, Hyderabad, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/16 (2006.01); G05B 9/02 (2006.01); G06F 11/30 (2006.01); G06F 13/12 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1641 (2013.01); G05B 9/02 (2013.01); G06F 11/0796 (2013.01); G06F 11/3055 (2013.01); G06F 13/122 (2013.01);
Abstract

Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.


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