The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

May. 09, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

David Hurley, Dublin, IE;

Ioan Domsa, Dublin, IE;

Ian Colgan, Dublin, IE;

Gerhardus Van Der Linde, Dublin, IE;

Patrick Hughes, Dublin, IE;

Maciej Burel, Dublin, IE;

Barry Clarke, Dublin, IE;

Mihaela Ioana Popovici, Haasrode, BE;

Lars-Ake Ragnarsson, Heverlee, BE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6684 (2013.01); H01L 21/02532 (2013.01); H01L 21/02554 (2013.01); H01L 21/02667 (2013.01); H01L 21/67098 (2013.01);
Abstract

A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.


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