The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 05, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Seungil Kang, Mountain View, CA (US);

Koohak Kim, Mountain View, CA (US);

Prasanna Srinivas, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06N 20/00 (2019.01); G06F 30/394 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/394 (2020.01); G06N 20/00 (2019.01); G06F 2119/02 (2020.01);
Abstract

Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design. The method also includes estimating parasitic information associated with the design based on the one or more output features, and outputting the parasitic information.


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Kang, Seungil. (2023). Machine learning based parasitic estimation for an integrated circuit chip design (U.S. Patent No. 11836435). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11836435

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