The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Jul. 15, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wan-Chen Chen, Hsinchu, TW;

Yu-Hsiung Wang, Zhubei, TW;

Han-Yu Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/94 (2006.01); H10B 43/50 (2023.01); H01L 49/02 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 28/87 (2013.01); H01L 28/88 (2013.01); H01L 28/91 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/66181 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/945 (2013.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.


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