The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Oct. 07, 2020
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventor:
Hock Chun Chin, Singapore, SG;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/11 (2006.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 51/20 (2023.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 43/50 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 29/40111 (2019.08); H10B 43/30 (2023.02); H10B 51/20 (2023.02); H01L 29/40117 (2019.08); H01L 29/78391 (2014.09); H01L 29/7926 (2013.01); H10B 43/35 (2023.02); H10B 43/50 (2023.02);
Abstract
A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOand the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.