The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Apr. 13, 2022
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Marcus Van Ierssel, Toronto, CA;
Prabhnoor Singh Kainth, Toronto, CA;
Nanyan Wang, Cupertino, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/107 (2006.01); H03L 7/093 (2006.01); H03L 7/08 (2006.01); H04L 7/02 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1075 (2013.01); H03L 7/0807 (2013.01); H03L 7/093 (2013.01); H04L 7/0079 (2013.01); H04L 7/02 (2013.01);
Abstract
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.