The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Aug. 31, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sai Bhushan, Greater Noida, IN;

Chirag Ahuja, North Melbourne, AU;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 20/00 (2019.01); H01L 23/00 (2006.01); G06F 30/33 (2020.01); G06F 18/214 (2023.01);
U.S. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 18/214 (2023.01); G06F 30/33 (2020.01); H01L 24/42 (2013.01); H01L 2924/14 (2013.01);
Abstract

The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design. Embodiments may include receiving, using at least one processor, at least one layout associated with the electronic design and separating the at least one layout into one or more grids. Embodiments may also include extracting one or more connectivity features from the one or more grids, wherein the one or more connectivity features include instance-pin and pin information. Embodiments may also include training a machine learning model, based upon, at least in part, the one or more connectivity features and receiving the machine learning model and a test layout at a predictor engine. Embodiments may further include providing a user with a pin placement recommendation based upon, at least in part, the machine learning model and the test layout.


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