The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Apr. 24, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vijay S. Ramesh, Boise, ID (US);

Phillip G. Hays, Anacortes, WA (US);

Craig M. Cutler, Monroe, WA (US);

Andrew J. Rees, Redmond, WA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/1081 (2016.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/3893 (2013.01); G06F 12/0246 (2013.01); G06F 13/1673 (2013.01); G06F 13/4221 (2013.01);
Abstract

Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. A first operand formatted in a universal number or posit format can be received by a first buffer resident on acceleration circuitry. A second operand formatted in a universal number or posit format can be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both can be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both can be received by a third buffer resident on the acceleration circuitry.


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