The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2023
Filed:
Mar. 25, 2021
Applicant:
Power Integrations, Inc., San Jose, CA (US);
Inventors:
Kuo-Chang Robert Yang, Campbell, CA (US);
Kamal Raj Varadarajan, Fremont, CA (US);
Sorin S. Georgescu, Gilroy, CA (US);
Assignee:
POWER INTEGRATIONS, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1066 (2013.01); H01L 29/1058 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01);
Abstract
Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (). MET gate and MET source () may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).