The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Jul. 19, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shiang-Bau Wang, Pingzchen, TW;

Li-Wei Yin, Hsinchu, TW;

Chen-Huang Huang, Hsinchu, TW;

Ming-Jhe Sie, Taipei, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/3065 (2013.01); H01L 21/76829 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.


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