The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Jan. 12, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Yao-Hsiung Kung, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/764 (2013.01); H01L 21/76897 (2013.01); H10B 12/0335 (2023.02); H10B 12/30 (2023.02); H10B 12/31 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02);
Abstract

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.


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