The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Feb. 25, 2021
Applicant:

Iix Inc., Tokyo, JP;

Inventors:

Makoto Hatakenaka, Tokyo, JP;

Takashi Sakamoto, Tokyo, JP;

Yoshihide Minegishi, Tokyo, JP;

Ryohei Hatta, Tokyo, JP;

Norimasa Senda, Tokyo, JP;

Assignee:

IIX INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2074 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

An input signal correction device includes an input circuit, extension circuit, degenerate circuit, separation circuit, recovery circuit and delay adjustment circuit that operate at an operating frequency f, demura circuit that operates at an operating frequency f/2, and adder circuit. The extension circuit extends the period of R and B input signals by a factor of 2 and outputs preprocessing signals, the degenerate circuit degenerates a G input signal, the demura circuit corrects preprocessing signals from the extension and degenerate circuits and outputs correction signals, the separation circuit reduces the period of the R and B correction signals to ½ and outputs differential signals, recovery circuit reduces the period of G correction signal to ½ and outputs the same differential signal over two periods, the delay adjustment circuit delays the input and output signals, and the adder circuit adds the differential signals to the delay signals and outputs output signals.


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