The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Dec. 20, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Vydhyanathan Kalyanasundharam, Sunnyvale, CA (US);

John Wuu, Fort Collins, CO (US);

Chintan S. Patel, San Antonio, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0895 (2016.01); G06F 13/16 (2006.01); G06F 12/0891 (2016.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0895 (2013.01); G06F 12/0811 (2013.01); G06F 12/0891 (2013.01); G06F 13/1668 (2013.01);
Abstract

A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.


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