The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Sep. 30, 2021
Applicant:

Advantest Test Solutions, Inc., San Jose, CA (US);

Inventors:

Karthik Ranganathan, San Jose, CA (US);

Samer Kabbani, San Jose, CA (US);

Gilberto Oseguera, San Jose, CA (US);

Ira Leventhal, San Jose, CA (US);

Koji Miyauchi, San Jose, CA (US);

Keith Schaub, San Jose, CA (US);

Amit Kucheriya, San Jose, CA (US);

Kotaro Hasegawa, San Jose, CA (US);

Yoshiyuki Aoki, San Jose, CA (US);

Assignee:

Advantest Test Solutions, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 1/02 (2006.01); G01R 1/04 (2006.01); G01R 1/067 (2006.01); G01R 1/073 (2006.01); G01R 31/27 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 1/0408 (2013.01); G01R 31/2834 (2013.01);
Abstract

A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.


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