The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Dec. 09, 2021
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Yong Li, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H10B 10/00 (2023.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/1083 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.


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