The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Apr. 05, 2022
Applicant:
Shinko Electric Industries Co., Ltd., Nagano, JP;
Inventors:
Yoshihisa Kanbe, Nagano, JP;
Toyoaki Sakai, Nagano, JP;
Assignee:
SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/10 (2006.01); H05K 3/42 (2006.01); H05K 3/06 (2006.01);
U.S. Cl.
CPC ...
H05K 3/108 (2013.01); H05K 3/064 (2013.01); H05K 3/423 (2013.01); H05K 2203/0143 (2013.01); H05K 2203/0554 (2013.01); H05K 2203/0582 (2013.01);
Abstract
A resist layer forming method includes a process of laminating a resist layer on a base at a first pressure using a laminate roller having a first temperature, and a process of pressing the resist layer against the base at a second pressure higher than the first pressure using a metal plate having a second temperature lower than the first temperature.
Kanbe, Yoshihisa. (2023). Resist layer forming method, method for manufacturing wiring board, and resist layer forming apparatus (U.S. Patent No. 11818847). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11818847
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile