The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Oct. 11, 2021
International Business Machines Corporation, Armonk, NY (US);
Mukta Ghate Farooq, Hopewell Junction, NY (US);
Katsuyuki Sakuma, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention discloses embodiments of a semiconductor chip with one or more bottom external (power or ground) connections, a front side power network layer, a device layer, and a grind side power network layer. The device layer has a plurality of devices. One or more of the devices has one or more device power connections and one or more device ground connections and the device layer has a front side and a back grind side. The front side power network layer has power, ground, signal, and other connections that connect to respective device power and device ground connections from/through the top front side layer. In like manner, power, ground, signal, and other connections connect to respective device power and device ground connections from/through the bottom of grind side power network layer. (Alternative, e.g., external conduit connections are disclosed.) Accordingly, one or more first device power connections is connected to one or more of the front side power network layer connections, one or more second device power connections is connected to one or more of grind side power network connections so the front side power network layer and the grind side power network layer provide the device layer with a dual power/ground feed/distribution from both the top/back and bottom/front of the device layer of the chip.