The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Feb. 25, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Aswin Thiruvengadam, Folsom, CA (US);

Daniel L. Lowrance, El Dorado Hills, CA (US);

Peter Feeley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G06F 12/02 (2006.01); G11C 16/10 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/028 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G11C 16/10 (2013.01); G06F 2212/7207 (2013.01); G11C 2029/4402 (2013.01);
Abstract

The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.


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