The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Nov. 24, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Chung-Pin Chou, Hsinchu, TW;
Chun-Wen Wang, Hsinchu, TW;
Meng Ku Chi, Hsinchu, TW;
Yan-Cheng Chen, Hsinchu, TW;
Jun-Xiu Liu, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06N 20/00 (2019.01); G06N 5/04 (2023.01); G06T 7/70 (2017.01); G06T 7/00 (2017.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01); G06T 7/001 (2013.01); G06T 7/70 (2017.01); G06T 2207/10061 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/30148 (2013.01);
Abstract
A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.