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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11816406 B1

PDFFull Text
Date of Patent:
Nov. 14, 2023

Filed:

Jun. 03, 2021

High-level synthesis (hls) method and apparatus to specify parallelism in computer hardware

Applicant:

Legup Computing Inc., Toronto, CA;

Inventors:

Jongsok Choi, Toronto, CA;

Ruolong Lian, Toronto, CA;

Andrew Christopher Canis, Toronto, CA;

Jason Helge Anderson, Toronto, CA;

Muhammad R. Soliman, Scarborough, CA;

Assignee:

MICROCHIP TECHNOLOGY INC., Chandler, AZ (US);

Attorneys:

Lance Kreisman

Peninsula Patent Group

Primary Examiner:

Suchin Parihar

Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 13/16 (2006.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 13/1673 (2013.01); G06F 30/3312 (2020.01);
Abstract

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.

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Choi, Jongsok. (2023). High-level synthesis (hls) method and apparatus to specify parallelism in computer hardware (U.S. Patent No. 11816406). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11816406

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