The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Apr. 02, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vidhya Krishnan, Folsom, CA (US);

Siddhartha Chhabra, Portland, OR (US);

David Puffer, Tempe, AZ (US);

Ankur Shah, Folsom, CA (US);

Daniel Nemiroff, El Dorado Hills, CA (US);

Utkarsh Y. Kakaiya, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1433 (2013.01); G06F 11/1004 (2013.01); G06F 12/0292 (2013.01); G06F 12/1408 (2013.01); G06F 12/1466 (2013.01); G06F 12/1483 (2013.01);
Abstract

Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.


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