The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Feb. 07, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tina C. Toupal, Portland, OR (US);

Shamsul Abedin, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 15/78 (2006.01); H04L 12/54 (2022.01); G06F 13/40 (2006.01); H04B 10/80 (2013.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0757 (2013.01); G06F 9/4812 (2013.01); G06F 13/4068 (2013.01); G06F 15/7807 (2013.01); H04B 10/801 (2013.01); H04L 12/5601 (2013.01);
Abstract

A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.


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