The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Mar. 25, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Skyler Arron Windh, McKinney, TX (US);

Allan Kennedy Porterfield, Durham, NC (US);

Douglas John Vanesko, Dallas, TX (US);

Randall Paul Meyer, Allen, TX (US);

Patrick Alan Estep, Rowlett, TX (US);

Bashar Romanous, Allen, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 8/453 (2013.01); G06F 8/433 (2013.01); G06F 8/451 (2013.01); G06F 8/457 (2013.01); G06F 8/458 (2013.01);
Abstract

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.


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