The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Jun. 02, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Cristian Pavao Moreira, Frouzins, FR;

Andreas Johannes Köllmann, Rosengarten, DE;

Ulrich Moehlmann, Moisburg, DE;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01S 7/40 (2006.01); H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31727 (2013.01); G01S 7/4008 (2013.01); G01S 7/4021 (2013.01); H03K 3/017 (2013.01);
Abstract

The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit () comprising: a clock signal generator () configured to provide an output clock signal () having a duty cycle; a duty cycle detector () arranged to receive the output clock signal () and provide an output flag if the duty cycle of the clock signal () is outside a predetermined range; a controller () arranged to provide a duty cycle select signal () to the clock signal generator () to cause the clock signal () to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector ().


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