The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Jun. 25, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyoung Lim Suk, Suwon-si, KR;

Seokhyun Lee, Hwaseong-si, KR;

Jaegwon Jang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/08 (2006.01); H01L 23/538 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0805 (2013.01); H01L 23/5222 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 28/60 (2013.01);
Abstract

Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.


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