The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2023
Filed:
Jan. 08, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Haitao Liu, Boise, ID (US);
Kamal M. Karda, Boise, ID (US);
Gurtej S. Sandhu, Boise, ID (US);
Sanh D. Tang, Boise, ID (US);
Akira Goda, Boise, ID (US);
Lifang Xu, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H10B 43/40 (2023.01); G11C 16/08 (2006.01); H01L 23/532 (2006.01); H01L 21/28 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/08 (2013.01); H01L 23/5329 (2013.01); H01L 29/40117 (2019.08); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02);
Abstract
A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.