The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2023
Filed:
Nov. 05, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
George Chung Fai Ng, Markham, CA;
Marcus Van Ierssel, Toronto, CA;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/089 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0891 (2013.01); H03L 7/099 (2013.01);
Abstract
A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.