IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11804547 B1

PDFFull Text
Date of Patent:
Oct. 31, 2023

Filed:

Aug. 24, 2021

Gate structure and method with enhanced gate contact and threshold voltage

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Max Liu, New Taipei, TW;

Yen-Ming Peng, Taoyuan County, TW;

Wei-Shuo Ho, New Taipei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/02667 (2013.01); H01L 21/30625 (2013.01); H01L 21/324 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

Find Patent Forward Citations

Loading…