The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Nov. 22, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Anthony D. Veches, Boise, ID (US);

Brian P. Callaway, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4074 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01); G11C 11/22 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G06F 13/1668 (2013.01); G11C 11/2297 (2013.01); H01L 23/5252 (2013.01); H01L 23/5256 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1441 (2013.01);
Abstract

Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.


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