The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Sep. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Herman Schmit, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01F 1/10 (2006.01); H03K 19/17764 (2020.01); H03K 19/17752 (2020.01); G06F 30/34 (2020.01); H03K 19/17736 (2020.01); H03K 19/1776 (2020.01); G06F 119/04 (2020.01); H03K 3/03 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17764 (2013.01); G06F 30/34 (2020.01); H03K 19/1776 (2013.01); H03K 19/17744 (2013.01); H03K 19/17752 (2013.01); G06F 2119/04 (2020.01); H03K 3/0315 (2013.01); H03K 19/17736 (2013.01);
Abstract

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.


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