The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Mar. 27, 2022
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Su Xing, Singapore, SG;

Chung Yi Chiu, Tainan, TW;

Hai Biao Yao, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8232 (2006.01); H01L 21/762 (2006.01); H01L 29/749 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/225 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78603 (2013.01); H01L 21/2253 (2013.01); H01L 21/762 (2013.01); H01L 21/8232 (2013.01); H01L 29/0653 (2013.01); H01L 29/66772 (2013.01); H01L 29/749 (2013.01);
Abstract

A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.


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