The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Aug. 11, 2021
Applicant:

Nuvoton Technology Corporation Japan, Kyoto, JP;

Inventors:

Yoshihiro Matsushima, Shiga, JP;

Yoshihiko Kawakami, Osaka, JP;

Shinya Oda, Osaka, JP;

Takeshi Harada, Kagoshima, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/78 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0657 (2013.01); H01L 21/78 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 μm; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 μm. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.


Find Patent Forward Citations

Loading…