The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Sep. 24, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Xiang Yang, Santa Clara, CA (US);

Kou Tei, San Jose, CA (US);

Ohwon Kwon, Pleasanton, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 25/065 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02);
Abstract

Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.


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