The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Dec. 16, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Masao Kondo, Nagaokakyo, JP;

Kiichiro Takenaka, Nagaokakyo, JP;

Satoshi Tanaka, Nagaokakyo, JP;

Takayuki Tsutsui, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/14 (2006.01); H03F 3/213 (2006.01); H03F 1/56 (2006.01); H05K 1/18 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H03F 3/213 (2013.01); H01L 23/66 (2013.01); H01L 24/16 (2013.01); H03F 1/565 (2013.01); H05K 1/181 (2013.01); H01L 2223/6655 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/30111 (2013.01); H03F 2200/222 (2013.01);
Abstract

A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.


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