The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jul. 28, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Saurabh Roy, Villach, AT;

Thomas Aichinger, Faak am See, AT;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/516 (2013.01); H01L 29/66053 (2013.01); H01L 29/78391 (2014.09);
Abstract

A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.


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