The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jul. 07, 2021
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Erwin Ian Vamenta Almagro, Lapu-Lapu, PH;

Maria Clemens Ypil Quinones, Cebu, PH;

Romel N. Manatad, Liloan, PH;

Maria Cristina Estacio, Lapu-Lapu, PH;

Elsie Agdon Cabahug, Consolacion, PH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49541 (2013.01); H01L 23/31 (2013.01); H01L 23/5226 (2013.01);
Abstract

Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).


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