The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Sep. 23, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bassel Daher, Nazareth, IL;

Ari-Shaul Leibman, Talmey Elazar, IL;

George Shchupak, Zviya, IL;

Or O Rotem, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/413 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 7/222 (2013.01); G11C 11/4074 (2013.01); G11C 11/413 (2013.01);
Abstract

An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.


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