The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jul. 14, 2021
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

John Eric Linstadt, Palo Alto, CA (US);

Brent Steven Haukness, Sunnyvale, CA (US);

Kenneth L. Wright, Sunnyvale, CA (US);

Thomas Vogelsang, Mountain View, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/403 (2006.01); G11C 11/4097 (2006.01); G11C 11/4096 (2006.01); G11C 8/08 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 5/02 (2006.01); G11C 11/408 (2006.01); G06F 12/06 (2006.01); G11C 11/406 (2006.01); G11C 11/409 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/403 (2013.01); G06F 12/06 (2013.01); G11C 5/025 (2013.01); G11C 7/1018 (2013.01); G11C 7/1045 (2013.01); G11C 7/1096 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 11/408 (2013.01); G11C 11/409 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01); G11C 11/4097 (2013.01); G11C 11/40618 (2013.01); G11C 11/4091 (2013.01);
Abstract

A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.


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