The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jun. 11, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Frederick Chen, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/8265 (2023.02); H10B 63/845 (2023.02); H10N 70/011 (2023.02);
Abstract

Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.


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