The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2023
Filed:
Jul. 03, 2022
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H10B 41/30 (2023.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H10B 41/42 (2023.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66545 (2013.01); H01L 29/66598 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H01L 29/7883 (2013.01); H10B 41/42 (2023.02); H01L 21/3213 (2013.01);
Abstract
A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.