The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jan. 21, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Tae Hoon Kim, Icheon-si, KR;

Chae Sung Lee, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3107 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.


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