The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jun. 04, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Li-Sheng Weng, San Diego, CA (US);

Charles David Paynter, Encinitas, CA (US);

Ryan Lane, San Diego, CA (US);

Jianwen Xu, San Diego, CA (US);

William Stone, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/73 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3171 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 25/105 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17163 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73209 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.


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