The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Dec. 01, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Choonghyun Lee, Kanagawa, JP;

Pouya Hashemi, Purchase, NY (US);

Takashi Ando, Eastchester, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/04 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823885 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02609 (2013.01); H01L 21/225 (2013.01); H01L 21/324 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01); H01L 29/04 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.


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