The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jun. 13, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Thuan Vu, San Jose, CA (US);

Stephen Trinh, San Jose, CA (US);

Stanley Hong, San Jose, CA (US);

Anh Ly, San Jose, CA (US);

Steven Lemke, Boulder Creek, CA (US);

Nha Nguyen, San Jose, CA (US);

Vipin Tiwari, Dublin, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G06N 3/063 (2023.01); G06F 3/06 (2006.01); G06N 3/08 (2023.01); G11C 16/26 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G06F 3/0688 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); G11C 29/10 (2013.01);
Abstract

In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.


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