The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Mar. 30, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Naveen Bhoria, Plano, TX (US);

Kai Chirca, Dallas, TX (US);

Timothy D. Anderson, University Park, TX (US);

Duc Bui, Grand Prairie, TX (US);

Abhijeet A. Chachad, Plano, TX (US);

Son Hung Tran, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/00 (2006.01); G06F 12/0897 (2016.01); G06F 12/0875 (2016.01); G06F 9/32 (2018.01); G06F 11/10 (2006.01); G06F 9/345 (2018.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3016 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 9/3834 (2013.01); G06F 9/3867 (2013.01); G06F 9/3877 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 12/0811 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01);
Abstract

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.


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