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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11778816 B1

PDFFull Text
Date of Patent:
Oct. 03, 2023

Filed:

Dec. 19, 2022

Etch method for opening a source line in flash memory

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yong-Sheng Huang, Taipei, TW;

Ming Chyi Liu, Hsinchu, TW;

Chih-Pin Huang, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Errol V Fernandes

Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H10B 41/30 (2023.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76892 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

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