The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Jul. 29, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Eric S. Carman, San Francisco, CA (US);

Durai Vishak Nirmal Ramaswamy, Boise, ID (US);

Richard E Fackenthal, Carmichael, CA (US);

Kamal M. Karda, Boise, ID (US);

Karthik Sarpatwari, Boise, ID (US);

Haitao Liu, Boise, ID (US);

Duane R. Mills, Shingle Springs, CA (US);

Christian Caillat, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H10B 12/00 (2023.01); H01L 29/24 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G11C 11/4094 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); H01L 29/24 (2013.01); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02);
Abstract

Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.


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